This course introduces the techniques of modeling digital systems at various levels of abstraction, and computer-aided design algorithms that are applied to these models to support design and analysis tasks. The course covers modeling through the use of a modern hardware description language (Verilog). The language is used to model an IC in the early stages of design using behavioral modeling techniques and in later stages using structural modeling techniques. This course is not a how-to course on using CAD tools. Rather it is a study of the algorithms used by CAD tools. The course will cover: modeling of digital systems for simulation and synthesis using Verilog; test generation which is used to determine if a manufactured design is correct; event-driven simulation algorithms, and physical design which is used to map the synthesized logic design onto physical IC area. 4 hrs. lec.
