Low-Power Clock Synchronization using
Electromagnetic Energy Radiating from AC Power Lines

Clock synchronization is highly desirable in many sensor networking applications. It enables event ordering, coordinated actuation, energy-efficient communication and duty cycling. This paper presents a novel low-power hardware module for achieving global clock synchronization by tuning to the magnetic field radiating from existing AC power lines. This signal can be used as a global clock source for battery-operated sensor nodes to eliminate drift between nodes over time even when they are not passing messages. With this scheme, each receiver is frequency-locked with each other, but there is typically a phase-offset between them. Since these phase offsets tend to be constant, a higher-level compensation protocol can be used to globally synchronize a sensor network. We present the design of an LC tank receiver circuit tuned to the AC 60Hz signal which we call a Syntonistor. The Syntonistor incorporates a low-power micro-controller that filters the signal induced from AC power lines generating a pulse-per-second output for easy interfacing with sensor nodes. The hardware consumes less than 58μW which is 2-3 times lower than the idle state of most sesor networking MAC protocols. Next, we evaluate a software clock-recovery technique running on the local micro-controller that minimizes timing jitter and provides robustness to noise. Finally, we provide a protocol that sets a global notion of time by accounting for phase-offsets. We evaluate the synchronization accuracy and energy performance as compared to in-band message passing schemes. The use of out-of-band signals for clock synchronization has the useful property of decoupling the synchronization scheme from any particular MAC protocol. Our experiments show that over a 11 day period, eight nodes distributed across the floor of the CIC building on Carnegie Mellon's campus remained synchronized on an average to less than 1ms without exchanging any radio messages beyond the initialization phase.

Why power-line synchronization?

Unlike other hardware-based clock synchronization solutions that require transmitters, our system is able to utilize the existing signals radiating from AC power-lines tens to hundreds of meters away. In contrast to systems like the WWVB atomic clock broadcast and GPS time receiver, our system operates extremely well indoors and around the periphery of buildings. Electromagnetic interference from power lines is so ubiquitous that most electronic devices including many radios are specifically designed to reject 50 and 60 Hz noise. We present the design of a low-cost and low-powered device called a Syntonistor which uses these induced signals to provide clock synchronization in wireless devices. By leveraging this highly available common clock source, we can now provide synchronization using significantly less power than existing message passing solutions. Furthermore, this source continues to operate even when nodes become disconnected from the network for extended periods of time.

Power Lines as a clock source

The frequency of an AC power line typically has a sta- bility of about 5 * 0^-5. In the past, devices like alarm clocks and home appliances have used a direct connection to the power-line as a source for keeping wall-clock time. In order for power to be delivered efficiently across the country, the phase difference between any two points should remain fairly constant. [9] shows the differential delay to have a stability of 1 part in 10^-8 over a 24 hour period. Hence, the power grid is phase-coherent. In the United States, there are four main power grids that cover the entire country. Most buildings are supplied with multiple phases of power. This in combination with the orientation between our receiver and nearby dominant magnetic fields, the detected signal will lead or lag with respect to the original signal resulting in a a phase offset. This means that our receivers achieve syntonization with each other. Syntonization is defined as when two clocks are frequency locked, but they may have a phase offset (hence we call our receiver a Syntonistor). Since the power lines act as a global broadcast, even if the frequency shifts, each node in the network still receives a common global clock tick. This means that after initialization, all clock rates are identical and do not drift.

Syntonistor Hardware

The circuit and block diagrams below show the major components of the Syntonistor. The power-line magnetic field is detected by an antenna composed of an inductor (L) and capacitor (C) tank circuit. The LC component of the circuit is tuned to a resonant frequency of 60H. Once the signal is captured, amplification requires an ex- tremely high input impedance, common mode rejection ratio (CMRR) and gain value typically found in an instrumenta- tion amplifier (INA). The output of the INA is passed through an AC-coupled transmission line that is configured as a high- pass filter removing DC bias from the signal. The AC signal is further amplified through a second stage using a TI OPA369 micro-power op-amp. A second OPA369 (located on the same IC package) is used to create a low- power bias voltage to center the 60 Hz signal helping to keep it within the linear operating range of the amplifier. A MCP4012 programmable rheostat is used to set the gain of the OPA369 to one of 64 different levels. The output from the OPA369 is passed directly to an analog input on a PIC12F683 micro-controller.

The PIC12F683 processor on the Syntonistor board is extremely low-powered and heavily resource constrained with just 128 bytes of RAM and 2048 bytes of FLASH. These scarce resources allow the CPU to operate with an idle and active current consumption of 50nA and 11μA respectively at 2 volts. The firmware running on this processor is responsible for three main tasks. First, the processor must slowly adjust the auto-gain level of the second stage amplifier to ensure that the signal is distinct enough to have noticeable zero-crossing points while not saturating in the presence of a strong signal. Next, the processor must filter the incoming pulses and generate a stable pulse per second (PPS) output which the sensor node can use for synchronization purposes. We desire a low-frequency output so as to not unnecessarily wake the main sensor node. Finally, the processor must toggle an error bit if it detects that the signal is no longer reliable. In the remainder of this section, we will discuss the various techniques used to achieve these goals.

Signal Conditioning

The signal received by the Syntonistor tends to suffer from jitter as well as occasional periods of lost reception. Filtering such a signal in the time domain to recover a clock is commonly solved using a Phase-Locked Loop (PLL). A PLL will generate its own local clock with a period that increases or decreases based on the measured phase difference between its local clock and the input clock. The rate at which the local clock is adjusted to match the input signal is a classical control problem. In our design, we implemented a proportional-integral (PI) PLL controller in software on the PIC processor. First, we perform a low-pass filter on the input signal. If an edge arrives too early or late, it is simply ignored. Since our target frequency is relatively constant (we assume that the 60Hz will not rapidly deviate), we chose to trade-off a slow convergence time with increasing stability. In the absence of an input signal, the PLL should be able to operate based on its local clock for a significant period of time.

Synchronization Protocol

A network-level protocol is used to fully synchronize the nodes. First the protocol uses an approach similar to the flooding time synchronization protocol [17] to establish an offset between each node's PPS edge and the master's notion of time. Once these offsets have been computed each node can maintain the difference between its incoming edge and the global notion of time. If the Syntonistor detects a significant error in the PLL's internal state, the device assumes an error and signals to the node that it should re-synchronize with its neighbors.


Anthony Rowe, Vikram Gupta, Raj Rajkumar, "Low-power Clock Synchronization using Electromagnetic Energy Radiating from AC Power Lines," 7th ACM Conference on Embedded Networked Sensor Systems (SenSys), November 2009. PDF (2.3Mb). (Updated version)


[9] Machlan H. Allan, D. Time transfer using nearly si- multaneous reception times of a common transmission. 26th Annual Symposium on Frequency Contro, pages 309-316, 1972.

[17] M. Maroti and B. Kusy and G. Simon and A. Ledeczi. The flooding time synchronization protocol. Proc. ACM Sensys, 2004.